Saleh Abdel-hafeez, Ph

A CMOS eight-transistor (8T) memory cell is used for a complete proposed SRAM design. The proposed output buffer, eliminating the use of sense amplifier with all its synchronization schemes, exploits a cost-effective of overhead circuitry, and more important reduces the power consumption by a rate of 43% in comparing to 6T SRAM. Furthermore, the cell contributes a silicon area of 30% larger than 6T SRAM cell. However, due to the elimination of conventional synchronization schemes that belongs to 6T structure, the 8T cell memory of sizes less than 20k-bit storage capacity has smaller total silicon area than six-transistor (6T) cell by a reduced rate of 6%, while it is larger by an increase rate of 13% otherwise. The simulation results show that, the embedded SRAM of size 128-Word x 128-bit is operating at a maximum frequency of 200 MHz for Write/Read clock cycle at 1.62 V power supply, and measures a total average power dissipation of 0.56 mW. All simulation results were conducted on 0.18 μm TSMC single poly and three layers of metals measuring a cell area of 2.2 x 3.0 μm 2 . 2. Double Data Rate Synchronization Using Delay-Locked Loop to the Order of Nano-second, 2011 Student: Laith Waleed Shahab Main Advisor: Dr. Saleh Abdel-hafeez Double data rate synchronization has become a key feature for deep sub-micron systems with increase mobility of computing and advances in Multi-Gbps throughput. An important loss of timing accuracy is attributed to the matching of various delay elements, where the Delay-locked Loop plays an important role to alleviate the problem. The DLLs are commonly used for clock synchronization in modern ICs because of their behavior in solving this type of problems with the advantages of superior stability and process portability. DLL circuitry incorporates very precise synchronization between data and reference clock. Subsequently, the delay-locked loop (DLL) is a circuit fed by a reference clock that attempts to minimize the jitter period of that reference clock by adjusting the delay of a variable delay buffers in a feedback loop, the delay buffer is a type of current source with CMOS inverter structure that is controlled by DLL phase difference signal. Consequently, the DLL design usually exploits the phase detector, charge pump, loop filter, and voltage controlled delay line (VCDL). The objective of this work is to design a DLL circuit in CMOS Technology level that minimizes the delay differences between data line and reference clock. The DLL exploits a novel feedback structure between data lines and clock in order to detect the phase difference between them in a form of current value. This minimization is considered as an essential circuit for Double Data Rate synchronization. The DLL circuit is required to synchronize the data rate at the Rising & Falling edges of reference clock down to 100 ps, where the expected clock may run at 500 MHz, this running frequency is usually used as standard for several DDR applications. The DLL CMOS circuit is realized in nanometer technology to the order of 150 nm. This technology is considered as a challenge for DLL circuit design due to biasing circuit, delay buffers and charge pump circuitries which require a large voltage for operations. The Nanotechnology exploits a feature of low power design since it operates at low voltage of 1.5 V and provides low parasitic capacitance at the gate and drain of CMOS transistor. 2. System and Method For Efficiency Implementing a Double Line Memory Architecture Using Nanotechnology Student: Mohammad Khair Shatnawi Main Advisor: Dr. Saleh Abdel-hafeez Double data rate (DDR) memories realize an I/O frequency up to twice that of conventional single data rate memory. Hence, DDR memories are desirable to maximize system ability and improve microprocessors performance. In this research, an efficient implementation of a double data rate (DDR) memory architecture using Eight-Transistors cell is presented. The proposed DDR memory architecture comprises a memory device that includes a memory core which is configured into even and odd cell rows, where each cell contains eight transistors (8T-cell). The 8T-cell is commonly known for its small silicon geometry with the advantage of supporting Nano-scale continued technology. The DDR memory of size 64x128 bit (1Kbyte) with 8T-cell is proposed for SPICE implementation using 90nm CMOS technology. Subsequently, the complete structure including a decoder and an I/O circuitry will be implemented and integrated with the memory core for SPICE simulations. All memory characteristics will be extracted and realized including timing analysis of setup-hold, access time, power dissipation and layout area. 3. Computer Architecture — DYNAMIC BRANCH PREDICTION SCHEMES AND PERFORMANCES, AUG. 2005 Student: Shatha Alhasan Main Advisor: Dr. Saleh Abdel-hafeez ABSTRACTIncreasing the amount of Instruction Level Parallelism (ILP) in any modern processor yields to an increase in the amount of stalls caused by the control dependences. To overcome these stalls, two categories of branch prediction were introduced to predict the outcome of the branch, rather than stalling waiting for the branch instruction to be calculated. Static branch prediction has low value of accuracy, while dynamic branch prediction techniques promise better results. This thesis studies some of these dynamic branch prediction techniques, and compare between them. SimpleScalar tool set is mainly adapted to it for computer architecture results. Some SPEC 95 and SPEC 2000 benchmarks are used to simulate the entire studied branch prediction schemes. Many dynamic prediction schemes are introduced and simulated. Some of these schemes depend on local branch information, while the other depend on local and global branch information. Two-bit counter branch predictor is one scheme that depends on local branch information only, but it has low prediction rate of about 66%. To improve the prediction rate, bimodal predictor was proposed; such that, it uses only local information with an average prediction rate of about 88%. Two-level predictors were also proposed to increase prediction rate, these predictors depend on both local and global branch information. One good implementation of two-level branch predictors is Gshare. This predictor with 14-bit branch history shift register has 91% prediction rate as an average of all the study simulation benchmarks. To further enhance branch prediction rate, two branch prediction schemes are combined, with a selector to choose between them. Gshare and bimodal predictors are combined, with two bit saturating counters to select the branch outcome. The average prediction rate of these combined schemes is 93%, which is higher than other dynamic branch prediction schemes for almost same Increasing the amount of Instruction Level Parallelism (ILP) in any modern processor yields to an increase in the amount of stalls caused by the control dependences. To overcome these stalls, two categories of branch prediction were introduced to predict the outcome of the branch, rather than stalling waiting for the branch instruction to be calculated. Static branch prediction has low value of accuracy, while dynamic branch prediction techniques promise better results. This thesis studies some of these dynamic branch prediction techniques, and compare between them. SimpleScalar tool set is mainly adapted to it for computer architecture results. Some SPEC 95 and SPEC 2000 benchmarks are used to simulate the entire studied branch prediction schemes. Many dynamic prediction schemes are introduced and simulated. Some of these schemes depend on local branch information, while the other depend on local and global branch information. Two-bit counter branch predictor is one scheme that depends on local branch information only, but it has low prediction rate of about 66%. To improve the prediction rate, bimodal predictor was proposed; such that, it uses only local information with an average prediction rate of about 88%. Two-level predictors were also proposed to increase prediction rate, these predictors depend on both local and global branch information. One good implementation of two-level branch predictors is Gshare. This predictor with 14-bit branch history shift register has 91% prediction rate as an average of all the study simulation benchmarks. To further enhance branch prediction rate, two branch prediction schemes are combined, with a selector to choose between them. Gshare and bimodal predictors are combined, with two bit saturating counters to select the branch outcome. The average prediction rate of these combined schemes is 93%, which is higher than other dynamic branch prediction schemes for almost same size. Predictor size is one main issue related to the predictor cost. Our study showed that predictors’ sizes differ from one scheme to the other; such that, gshare predictor has the least size and PAP predictor has the largest size. The choice of the optimized predictor for each benchmark, with respect to predictor size, led us to choose gshare predictor. For gcc00 benchmark, the predictor with the best performance (92%) was GAP predictor with 13-bit BHSR. On the other hand, if gshare was chosen, with 13-bit BHSR, the prediction accuracy would be 91.1% but with half the size of Gap predictor. 3. VLSI Design for Network Security HARDWARE DESIGN OF AES S-BOX USING PIPELINING STRUCTURE OVER GF((2 4 ) 2 ), 2007 Student: Ahmad Sawalmeh Main Advisor: Dr. Saleh Abdel-hafeez ABSTRACTThe computer technology becomes part of our daily life, and the information flow through the internet becomes very huge, some of these data are sensitive and must be kept secure. Therefore, the need for secure electronic data exchange will become increasingly more important. For this reason many encryption algorithms have been developed for data security; such as, DES, Blowfish, and AES. The computer technology becomes part of our daily life, and the information flow through the internet becomes very huge, some of these data are sensitive and must be kept secure. Therefore, the need for secure electronic data exchange will become increasingly more important. For this reason many encryption algorithms have been developed for data security; such as, DES, Blowfish, and AES. In this thesis, the implementation of a shared and pipelined S-BOX architecture is proposed where a multiplicative inverter is reused and affine transformation is merged between SubByte and InvSubByte. A complete pipelined S-BOX in a behavioral model is implemented, followed by a synthesizable RTL-HDL model. The resulting speed, throughput, power, and implementation area are evaluated and compared with exsiting hardware implementations. The simulation and synthesis results confirm that, in general, the speed up for fully pipelining AES is 9.94 times higher in throughput than general AES without pipelining, but the area is 10 times larger than the general AES without pipelining (iterative looping). In contrast, the speed up for our proposed AES design is 11.78 times faster than general AES without pipelining, but area is only 2.5 times larger than the general AES without pipelining (iterative looping)